1. Field of the Invention
The present invention generally relates to a method for reducing non-uniformity or topography variation in a process for manufacturing semiconductor integrated non-volatile memory devices.
More specifically the invention relates to a method for reducing thickness non-uniformity between a cell array area and a peripheral circuit area during the manufacturing of the circuitry's gate structures after the floating gate structures, or part of them, of the cell array have been realized on the active regions of the semiconductor substrate.
It is well known in the art that, in memory devices realized with technologies requiring dimensions at 0.15 μm or less, thickness non-uniformities between the array and circuitry areas are of increasing importance, in particular in the case of high density memory devices and in the case of so-called multilevel memory devices.
Thickness non-uniformities between array and circuitry areas affect the subsequent process capabilities of lithography and etch to control and define the devices dimensions, especially in the array area. This in turn affects the performances of the whole memory device in the electric detection of the bit stored in the cell's array.
Without any limitation of the scope of the invention and with the only aim of simplifying its disclosure, the following description is given with reference to the process steps for manufacturing the gate structures in the array and circuitry areas of a flash memory device, for example a flash EEPROM memory device. In these memory devices the semiconductor memory cells of the array area use a floating gate to store charges thereon.
In fact the method of the invention can be applied in those cases where thickness non-uniformity between the array and circuitry areas may occur. In particular, it can be applied in those cases where other solutions to improve the processes to define the dimensions of each and every point in the array area, for instance lithographic and etching processes fail or become unfeasible, not suitable, or unreliable, or require the application or development of new materials and new technologies.
2. Description of the Related Art
As is well known to those skilled in the art, most non-volatile memory cells, particularly EPROM, flash EPROM or EEPROM, are formed in a semiconductor substrate using stacked-gate MOS transistors. The memory cells have a floating gate electrode to store charges and a control gate electrode to select the cell in the same way the single gate does in conventional MOS transistors. The term “floating” refers to the fact that no electrical connection exists to this gate.
Typically, the control gate electrode is stacked on the floating gate electrode and two different layers of conductive materials are used to form the double gate structure of the memory cell. A dielectric layer is provided to isolate the two gate layers.
Typically, the conductive material for the double gate structure is polysilicon, while for the dielectric layer, conventionally also called interpoly dielectric, composite films of SiO2/Si3N4/SiO2, Oxide/Nitride/Oxide, often referred to as ONO layers, are generally used, mainly for increased capacitive coupling between the two gate electrodes.
The memory cells are usually organized in a two-dimensional matrix, forming the cell array area. Rows and columns in fact form rectangular arrays. At the intersections of rows and columns, memory cells are realized, so that each cell is capable of storing a binary bit of data.
The columns typically represent the bit lines, while the rows define the word lines and addresses are assigned to each row or column. The process steps to manufacture such memory cells are well known from the prior art and the literature, and reference is made to the book by: S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era”, Lattice Press, Vol. 2, pg. 632–635.
Besides the cell array area, non-volatile memory devices comprise several other circuit blocks that generally surround the cell array area and form the peripheral circuit area. In the peripheral circuit area, the circuitry typically comprises MOSFET structures to perform operations like programming, reading, erasing and so on. As known and described for instance in the U.S. Pat. No. 6,353,243, MOSFETs are for example the building blocks of row decoder circuits that are responsible for selecting specific rows of memory cells within the cell array. MOSFETs are single gate transistors and their gate electrodes are typically made of polysilicon.
All process steps needed to build and define the cell array area and the circuitry area in non-volatile memory devices are well known to those skilled in the art.
The state of the art process to manufacture an array and circuitry of, for example, a flash EEPROM can be summarized as follow, also with reference to the enclosed FIGS. 1–4.
On a common silicon substrate (1) the active areas for both the memory cell array and the circuitry are first realized.
In its simplest form, the subsequent process of manufacturing the double gate structure of the memory cells and the single gate structure of the associated circuitry can be described in a sequence of steps as follow:                1. Forming a tunnel oxide film (2) on the active regions;        2. Depositing a polysilicon layer (3), indicated as Poly1 or P1 in FIG. 1: this layer is used for the floating gate electrode. The polysilicon layer 3 is to be kept only in the array while it is to be removed from the circuitry, as illustrated in FIG. 2.        3. Depositing a dielectric layer, the interpoly dielectric (4), which is generally a composite film of Oxide/Nitride/Oxide, the so-called “ONO” layers;        4. Patterning and etching (typically dry etching) the interpoly dielectric layer 4 and the polysilicon layer 3, to define the floating gate electrode of the memory cells, according to the mask pattern that defines the two-dimensional matrix of the cell array area (MATRIX mask, as illustrated in FIGS. 3 and 3a);        5. Forming one or more gate oxide layers;        6. Depositing a second polysilicon layer (5), according to FIG. 4. This layer is used for forming both the control gate electrodes in the array and the single gate electrodes in the circuitry;        7. Patterning and defining the dual-polysilicon-gate structure of the memory cells in the matrix, using a so-called self-aligning mask;        8. Patterning and defining the single gates of the MOSFETs in the circuitry, using a so-called circuitry mask.        
The manufacturing process continues with the subsequent formation of contacts and metal interconnects.
One of the issues that emerges from the process steps of creating the gate structures in the cell array area and in the circuitry area, as it has been just described, is related to the thickness differences between the total stack deposited to realize the double gate structure of the memory cells and the stack that forms the single gate structure in the circuitry.
In fact what happens is that generally the thickness of the second polysilicon layer, which is used for creating both the control gate of the memory cell in the array area and the single gate of the transistors in the circuitry area, cannot compensate for the thickness of the stack that is already in place for the memory cells.
In the specific case of this simplified example, by summing up the thicknesses of the different layers forming the memory cell, i.e. the stack made of the tunnel oxide, the first polysilicon layer, the interpoly dielectric and the second polysilicon layer in the array reaches a typical height of about 4000–4200 Å. On the other hand, in the circuitry area, the stack formed by the gate oxide and the second polysilicon layer builds up a total height of 2500–2700 Å.
Therefore a thickness in excess of about at least 1500 Å exists for the structures in the array with respect to the structures in the circuitry. This creates a “step” between the two structures.
The existence of such a step between the array area and the circuitry area is the source of severe issues and limitations in the process capabilities and reliabilities in the subsequent manufacturing steps.
Problems arise for example during the spinning of the antireflective coatings (BARC) and the subsequent application of the photoresist.
In fact, the antireflective coating is applied directly to the substrate and the resist is spun on top of it. Patterns are developed according to the specific mask layout, due to lithographic techniques, into the photoresist film and, if that is the case, into the BARC, in order to make possible the subsequent transfer of said patterns and the definition of the structures onto the deposited layers by etching.
As known in the art, see for instance the book by: S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era”, Lattice Press, Vol. 1, pg. 430–446, BARC and resist coating steps represent critical phases in the integrated circuit manufacturing process. The coating steps produce a uniform, adherent film of desired thickness over the entire wafer and across the different device areas. In order to maintain reproducible dimensions and linewidth in device fabrication applications, photoresist film uniformity across the wafer and all over the different device areas should be within about ±100 Å.
Lack of uniformity in BARC and resist coating leads hence to the co-existence of:                Regions with the correct desired thickness (within process specifications), where the lithographic process is capable of and reliable in defining the required dimensions and linewidths;        Other regions characterized by BARC and/or photoresist fims with thicknesses outside the process specifications, i.e. thicker or thinner than required, so that, during the exposure of the lithographic process, photoresist linewidth variations occur due to a local “out of focus” situation.        
An “out of focus” situation, with consequent photoresist linewidth variations, is the main source of irregularities in the definition of the gate dimensions, causing the latter to be outside the process and device specifications.
A typical effect, often observed by those skilled in the art, is a dimensional loss of the gate structures in the cell array (below the standard) that severely impacts the correct functioning of the memory device.
Demanding requirements to shrink the critical dimensions at 0.15 μm or below often find their limit in the capability of the lithographic process sequences to minimize linewidth variation over steps, and the case of thickness non uniformity in non volatile memory devices between array and circuitry is particularly evident.
A variety of procedures have been investigated to improve the lithographic process, in order to prevent or minimize the effects of those steps, like the introduction of thick resist layers, post exposure bakes, the use of special antireflective coatings and so on: reference is still made to the book by S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era”, Lattice Press, Vol. 1, pg. 440–442.
As well known to those skilled in the art, special photoresists and antireflective coatings are today available to offer a deposition process characterized by the particular property of conformity of the deposited film.
Although those special materials represent an improvement of the actual situation, on the other hand they also require the introduction of new lithographic technologies and/or new type of etching processes that increase the process complexity.
Unfortunately most of those special photoresists and antireflective coatings, together with the technologies and the processes for their use, are still in the research or in the development phase, and are therefore not suitable for industrial production.
Except for the on-going development and introduction of those new materials, however, it appears that no solutions have yet been provided to the technical problem of the limitations in the lithographic process capabilities to minimize dimensions and linewidth variations over steps, particularly when the steps are in relationship with the thickness non-uniformity between a cell array area and a peripheral circuit area of non-volatile memory devices.
Moreover, no solutions have been provided that are:                free of specific requirements or limitations for the material to use;        compatible with the conventional lithographic and etch processes;        compatible with the current manufacturing process flow limiting the increase in process complexity; and        have negligible influence on subsequent manufacturing steps.        
Thus, in the semiconductor manufacturing field there exists a strong need for providing a method of manufacturing a semiconductor integrated non-volatile memory device wherein the non-uniformity between array and circuitry areas is reduced, where said non-uniformity may cause lack of dimensional control and linewidth variation in the lithographic and etch patterning processes of the gate stacks, i.e. the formation of the control gate in the array and the single gate in the circuitry.
In particular, the aim of the present invention is providing a method to minimize the step or to reduce the difference in thicknesses that are evident from the prior art at the moment the substrate reaches the lithographic and etch patterning process steps that define simultaneously the control gate structure in the array and the standard gate structure in the circuitry.
Another goal of the present invention is to prevent linewidth and critical dimension variations across the wafer and across the device, in particular between cell array area and a peripheral circuit area, before the wafers reach the process steps that define and create the structure of the control gates in the cell array and of the single gate in the peripheral circuitry.